Power consumption in a computer system or a data processing device which includes a central processing unit (CPU), a memory and a group of peripheral units is always a significant concern. A power supply must be designed in the device to adequately power each unit. For example, the memory in the system is generally constituted by dynamic RAM (random access memory) and ROM (read only memory). When in use, power should be continually supplied to the RAM memory to sustain the information stored in the memory because of the volatile nature of the DRAM. The CPU should also be maintained fully powered during the operation of the system as it is the central unit in the system to control and manage every operation within the system including input/output operations by the peripheral units, information read and/or write operations in the memory and the data processing operations conducted by the CPU itself.
Aside from the capability of the power supply to provide ample power to power the units in the system, heat dissipation, physical size, weight, efficiency, and other related characteristics are paramount in designing or selecting the power source. These characteristics are exceptionally critical when the system the power supply is to support is a portable unit.
There are, in the prior art, many schemes for monitoring and controlling the consumption of power to a data processing device or devices when full operation is not desired or necessary. Many of them, nevertheless, are directed to power conservation of the memory unit of the device as it appears that the memory unit consumes considerable amounts of power. A number of known prior art references for monitoring and controlling the power consumption for a memory device are listed as follows:
1. U.S. Pat. No. 4,019,068, issued Apr. 19, 1977 for Low Power Output Disable Circuit For Random Access Memory; PA0 2. U.S. Pat. No. 4,151,611, issued Apr. 24, 1979 for Power Supply Control System For Memory System; PA0 3. U.S. Pat. No. 4,381,552, issued Apr. 26, 1983 for Standby Mode Controller Utilizing Microprocessor; PA0 4. U.S. Pat. No. 4,712,196, issued Dec. 8, 1987 for Data Processing Apparatus. PA0 1. U.S. Pat. No. 4,074,351, issued Feb. 14, 1978 for Variable Function Programmed Calculator; PA0 2. U.S. Pat. No. 4,293,927, issued Oct. 6, 1981 for Power Consumption Control System For Electronic Digital Data Processing Devices; PA0 3. U.S. Pat. No. 4,279,020, issued Jul. 14, 1981 for Power Supply Circuit For A Data Processor; PA0 4. U.S. Pat. No. 4,409,665, issued Oct. 11, 1983 for Turn-Off-Processor Between Keystrokes; PA0 5. U.S. Pat. No. 4,611,289, issued Sep. 9, 1986 for Computer Power Management System; PA0 6. U.S. Pat. No. 4,615,005, issued Sep. 30, 1986 for Data Processing Apparatus With Clock Signal Control By Microinstruction For Reduced Power Consumption And Method Therefor.
It shall be noted that in some of these schemes more or less of the CPU's participation is required to remove the power supply from the memory unit when it is not accessed. It is, therefore, critical to keep the CPU powered so that the CPU can simultaneously respond to any request for the CPU's operation including monitoring any user input at any time.
However, for most of the time, the CPU idles, doing nothing but waiting for a memory operation or an input/output operation of the peripheral units. As it is impossible to utilize a simple on/off switch for CPU power consumption, other circuitry solutions to the problem have been proposed and one which can be described as having a "sleeping mode" for a CPU is referred to in the above mentioned U.S. Pat. No. 4,381,552 for Standby Mode Controller Utilizing Microprocessor. The apparatus disclosed in the reference generates a WAIT signal to the CPU when full operation is not required to put the CPU in a standby mode where power consumption is reduced. During this period, sampling occurs at intervals in order to activate the device fully when full operation is required. However, the disadvantage of such solution is that CPU still needs to be powered in the standby mode and any request for full power operation occurred between the sampling intervals has to wait until the next sampling pulse generated to bring the CPU to full power operation.
In order to bring the power consumption of a CPU down to a minimum, a sophisticated power consumption arrangement is necessary in a computer system or a data processing device for providing power to the CPU only when it requires such power and removing power from CPU when the device is not in full operation while still keeping the power supply to every other unit in the system so that the CPU power-off is transparent to users.
A number of prior art references have also been known for monitoring and controlling the power consumption to a device or to a portion of a device including a means for providing a turn-off function when user interaction from a peripheral device to the device has not occurred for a given time period. However, these references pertain to the simpler calculator technology and fail to disclose the unique power consumption arrangement for a central processing unit (CPU) in a computer system. The references are listed as follows: